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? e98220c0z-te sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage av dd , dv dd 7v input voltage vin digital output pins dv dd +0.5 to dv ss ?.5 v other pins av dd +0.5 to av ss ?.5 v storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 3.0 to 5.5 v | dv ss ?v ss | 0 to 100 mv reference input voltage v arb , v brb , v crb 0 or more v v art , v brt , v crt 2.7 or less v analog input ain, bin, cin 1.7 vp-p or more clock pulse width tpw1, tpw0 9 ns (min.) to 1.1 ? (max.) operating ambient temperature topr ?0 to +85 ? description the CXD2303AQ is an 8-bit 3-channel cmos a/d converter for video with synchronizing digital clamp function. the adoption of 2 step-parallel method achieves low power consumption and a maximum conversion rates of 50 msps. features resolution : 8 bit?/2 lsb (dl) maximum sampling frequency : 50 msps low power consumption : 400 mw (at 50 msps typ.) (reference current excluded) synchronizing digital clamp function clamp on/off function reference voltage self-bias circuit input cmos/ttl compatible 3-state ttl compatible output single 5 v power supply or dual 5 v/3.3 v power supplies low input capacitance 15 pf reference impedance : 370 ? (typ.) different digital output multiplex format: ?4 : 4 : 4 format ?4 : 2 : 2 format ?4 : 1 : 1 format applications wide range of applications that require high-speed a/d conversion such as monitor, tv and vcr. structure silicon gate cmos ic 8-bit 3-channel 50 msps video a/d converter with clamp function 80 pin qfp (plastic) CXD2303AQ
? CXD2303AQ block diagram 1 2 12 11 23 22 35 42 41 68 62 71 30 29 27 25 24 40 38 36 28 26 31 32 39 37 34 33 70 69 67 66 64 63 decoder 13 72 50 49 21 47 46 80 73 10 3 44 20 45 60 65 61 58 43 59 54 53 51 57 52 data selector + latch 9 9 8 8 9 8 arts art ain arb arbs aio brts brt bin brb brbs bio crts crt cin crb crbs cio av ss av ss av ss av dd av dd av dd av dd av dd av dd dv dd dv dd dv dd dv dd dv ss dv ss dv ss dv ss a0 (lsb) a7 (msb) xaoe b0 (lsb) b7 (msb) xboe c0 (lsb) c7 (msb) xcoe tgr ctl0 ctl2 sy av ss av ss av ss clk cle clp sel ref0 ref3 test test 9-bit dac a-ch 8-bit adc digital clamp circuit digital clamp circuit 9-bit dac b-ch 8-bit adc digital clamp circuit 9-bit dac c-ch 8-bit adc clamp control
3 CXD2303AQ pin configuration 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 46 45 44 43 42 59 60 61 62 63 50 51 52 53 54 55 56 57 58 64 49 47 48 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 brbs brb av ss bin bio av dd brt brts arts art av dd aio ain av ss arb arbs av ss cin cio av dd crt crts dv ss dv ss c0 c1 c2 c3 c4 c5 c6 c7 dv dd dv dd b0 b1 b2 b3 b4 b5 b6 b7 dv ss dv ss a0 a1 a2 a3 a4 a5 a6 a7 tgr dv dd dv dd av ss crb crbs av dd av ss av ss test cle ref3 ref2 ref1 ref0 clp clk sel sy ctl2 ctl1 ctl0 xcoe xboe xaoe test av dd av dd
4 CXD2303AQ pin description pin no. symbol i/o equivalent circuit description 1, 2, 22, 23 13 to 20 3 to 10 73 to 80 21 11, 12, 71, 72 24, 27, 38, 60, 61, 65 25 40 63 26 39 64 31 34 69 32 33 70 28 37 66 dv dd a0 to a7 b0 to b7 c0 to c7 tgr dv ss av ss arbs brbs crbs arb brb crb art brt crt arts brts crts ain bin cin o o i dv dd dv ss digital power supply. +5 v or +3.3 v digital output. a0 (lsb) to a7 (msb) b0 (lsb) to b7 (msb) c0 (lsb) to c7 (msb) trigger output. see the tables and timing chart ii described in the output format section. digital ground. analog ground. shorting these pins to av ss generates voltage of about 0.5 v at the arb, brb and crb pins. reference voltage (bottom). reference voltage (top). shorting these pins to av dd generates voltage of about 2.5 v at the art, brt and crt pins. analog input. av dd av ss 26 40 39 34 33 32 69 63 31 rt 70 64 rb 25 rref av dd av ss 28 37 66
5 CXD2303AQ pin no. symbol i/o equivalent circuit description 29 36 67 30, 35, 41, 42, 62, 68 43 59 44 45 46 47 48 49 50 aio bio cio av dd test xaoe xboe xcoe ctl0 ctl1 ctl2 sy o i i i i av dd av ss 29 36 67 about 200 ? analog output. the digital clamp circuit comprises a d/a converter whose outputs are available on these pins. analog +5 v power supply. normally open. pull-down resistors are incorporated. output enable input. when these pins are low, data is output from the digital output pins. when these pins are high, the digital output pins are high impedance. the a, b and c channels can be controlled separately. also, these pins are not synchronized with the clock signal. pull-down resistors are incorporated. determines the digital output mode. see the mode tables and timing charts. pull-down resistors are incorporated. controls the digital output mode switching timing. the mode is switched by detecting the transition point where this pin changes from low to high. see the mode tables and timing charts for details. a pull-down resistor is incorporated. av dd av ss
6 CXD2303AQ pin no. symbol i/o equivalent circuit description 51 52 53 54 55 56 57 58 sel clk clp ref0 ref1 ref2 ref3 cle i i i i i av dd av ss controls the clp signal polarity. when this pin is low, clp is high active. when this pin is high, clp is low active. this pin has a built-in pull-down resistor. clock input. a pull-down resistor is incorporated. clamp pulse input. the polarity can be set to either high or low by setting sel. this pin has a built-in pull-down resistor. determines the clamp circuit reference data. see the mode tables for the set data. these pins are not synchronized with the clock input signal. pull-down resistors are incorporated. clamp enable. when this pin is low, the clamp circuit does not operate. when this pin is high, the clamp circuit operates. a pull-down resistor is incorporated.
7 CXD2303AQ digital output the following table shows the relationship between analog input voltage and digital output code. input signal voltage v art , v brt , v crt : : : : v arb , v brb , v crb step 0 : 127 128 : 255 digital output code msb lsb 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 : 0 0 0 0 0 0 0 0 timing chart i timing chart i -1. timing chart i -2. tr 4ns tf 4ns 90% 10% 3v 0v 1.3v 3v 0v t h t s 2.2v 0.8v 0.7v dd 0.3v dd tp lh , tp hl clock input digital input digital output 90% 10% 3v 0v 1.3v tr=4.5ns tf=4.5ns 10% tp hz tp zh 1.3v tp zl tp lz v oh v ol ( dv ss ) 1.3v 90% v oh ( dv dd ) v ol xaoe xboe xcoe output 1 output 2 input
8 CXD2303AQ 1.3v tpw1 tpw0 tsd n n+1 n+2 n+3 n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n 5n 4n 3n 2n 1 n n+1 n+2 n+3 n+4 n+5 n+6 4.5clk clock input analog input digital output : analog signal sampling point timing chart i -3
9 CXD2303AQ electrical characteristics analog characteristics (fc=50 msps, av dd =5 v, dv dd =3 to 5.5 v, v rb =0.5 v, v rt =2.5 v, ta=25 c) item conversion rate analog input band width differential non-linearity error integral non-linearity error offset voltage ( ? 1) differential gain error differential phase error sampling delay clamp offset voltage full-scale input ratio ( ? 2) signal-to-noise ratio spurious free dynamic range cross talk symbol fc bw e d e l e ot e ob dg dp tsd e oc snr sfdr ct conditions av dd =4.75 to 5.25 v ta= 40 to +85 c v in =0.5 to 2.5 v f in =1 khz triangular wave envelop 1 db r in =33 ? 3 db end point potential difference to art, brt, crt potential difference to arb, brb, crb ntsc 40 ire mod ramp, fc=14.3 msps v in =dc ref. data= c in =10 f 00010000 tpcw=2.75 s f c =14.3 mhz ref. data= f clp =15.75 khz 10000000 f in =150 khz f in =500 khz f in =1 mhz f in =3 mhz f in =10 mhz f in =20 mhz f in =150 khz f in =500 khz f in =1 mhz f in =3 mhz f in =10 mhz f in =20 mhz f in =1 mhz sin wave min. typ. max. unit 0.5 50 msps 60 mhz 100 0.3 0.5 lsb 0.7 1.5 50 10 mv 040 3% 1.5 deg 3ns 1 lsb 1 0.5 % 43 42 42 db 41 38 35 59 59 55 db 49 44 41 52 db ( ? 1) the offset voltage e ob is a potential difference between arb, brb, crb and a point of position where the voltage drops equivalent to 1/2 lsb of the voltage when the output data changes from 00000000 to 00000001 . e ot is a potential difference between art, brt, crt and a potential of point where the voltage rises equivalent to 1/2 lsb of the voltage when the output data changes from 11111111 to 11111110 . ( ? 2) full-scale input ratio = (2 v+e ot e ob ) of each channel 1 100 (%) average of (2 v+e ot e ob ) of each channel
10 CXD2303AQ dc characteristics (fc=50 msps, av dd =5 v, dv dd =5 v or 3.3 v, v rb =0.5 v, v rt =2.5 v, ta=25 c) item analog digital supply current analog digital reference current reference resistance (rt to rb) self-bias analog input resistance input capacitance output capacitance digital input voltage digital input current digital output current symbol i ad +i dd i ad i dd i ad +i dd i ad i dd i ref r ref v rb1 v rt1 v rb1 r in c ai1 c ai2 c din c ao c do v ih v il i ih i il i oh i ol i oh i ol i ozh i ozl conditions dv dd =5 v dv dd =3.3 v ntsc ramp dv dd =5 v wave input dv dd =3.3 v cle=low for every channel for every channel shorts av ss and arbs, brbs, crbs. shorts av dd and arts, brts, crts. fc=50 mhz ain, bin, cin fc=35 mhz fc=20 mhz ain, bin, cin, v in =1.5 v+0.07 vrms arts, art, arb, abfs, brts, brt, brb, brbs, crts, crt, crb, crbs digital input pin aio, bio, cio digital output pin av dd =4.75 to 5.25 v dv dd =3 to 5.5 v ta= 40 to +75 c vi=0 v to av dd ta= 40 to +75 c xoe=0 v voh=dv dd 0.8 v dv dd =5 v vol=0.4 v ta= 40 to 75 c xoe=0 v voh=dv dd 0.8 v dv dd =3.3 v vol=0.4 v ta= 40 to 75 c xoe=3 v voh=dv dd dv dd =3 to 5.5 v ta= 40 to 75 c vol=0 v min. typ. max. unit 80 100 70 90 510ma 70 90 60 80 510 4.1 5.4 7.7 ma 260 370 480 ? 0.50 0.54 0.58 v 1.80 1.92 2.04 13 16 k ? 30 15 pf 9 9 11 pf 11 2.2 v 0.8 40 240 a 2 4 ma 1.2 2.4 40 40 a ntsc ramp wave input cle=high f clp =15.75 khz
11 CXD2303AQ timing (fc=50 msps, av dd =5 v, dv dd =5 v or 3.3 v, v rb =0.5 v, v rt =2.5 v, ta=25 c) dc characteristic (continue) item output data delay tri-state output enable time tri-state output disable time setup time hold time pulse width symbol tp lh tp hl tp lh tp hl tp zh tp zl tp zh tp zl tp hz tp lz tp hz tp lz t s t h t h conditions dv dd =5 v c l =15 pf xoe=0 v dv dd =3.3 v r l =1 k ? dv dd =5 v c l =15 pf xoe=3 v 0 v dv dd =3.3 v r l =1 k ? dv dd =5 v c l =15 pf xoe=0 v 3 v dv dd =3.3 v ctl0 to 2, clp, sy clk conversion clp sy min. typ. max. unit 4.5 8.5 11.0 7.4 ns 3.8 10.0 13.8 6.7 4.2 7.1 11.3 8.0 ns 3.5 8.4 12.8 7.2 3.6 6.8 9.5 6.3 ns 2.9 6.8 10.5 6.0 3.5 ns 4.5 ns 2 cycle 1 electrical characteristics measurement circuit output data delay measurement circuit tri-state output measurement circuit c l to output pin measurement point c l to output pin r l r l measurement point dv dd note) c l includes capacitance of probes. conditions xoe=0 v i oh = 2 ma dv dd =5 v ta= 20 to 75 ci ol =4 ma xoe=0 v i oh = 1.2 ma dv dd =3.3 v ta= 20 to 75 ci ol =2.4 ma item digital output voltage symbol v oh v ol v oh v ol min. typ. max. unit dv dd 0.8 0.4 v dv dd 0.8 0.4
12 CXD2303AQ integral non-linearity error analog input resistance measurement circuit differential non-linearity error measurement offset voltage circuit differential gain error measurement circuit differential phase error digital output current measurement circuit dvm +v v a in a8 to a1 a0 b8 to b1 b0 ab comparator 8 s1 s2 s1 : on if aa buffer 8 1 clk (50mhz) controller 8 000 00 to 111 10 b in c in 8 8 a b c 8 0 a rt , b rt , c rt a in , b in , c in a rb , b rb , c rb clk av dd , dv dd av ss , dv ss +5v 0.5v a v 2.5v dut CXD2303AQ a in 8 b in c in 8 8 a b c 8 ttl ecl amp 2.5v 0.5v 40 ire modulation burst sync 100 0 40 ire ntsc signal source 620 5.2v 8 cx20202a-1 vector scope d.g d.p. s.g. (cw) ttl ecl fc clk 620 5.2v 10-bit d/a dut CXD2303AQ a rt , b rt , c rt a in , b in , c in a rb , b rb , c rb clk av dd, dv dd av ss, dv ss 2.5v oe 0.5v data out a i ol v ol a rt , b rt , c rt a in , b in , c in a rb , b rb , c rb clk 2.5v oe 0.5v data out a i oh v ol av dd, dv dd av ss, dv ss +4.75v +4.75v
13 CXD2303AQ description of operation 1. output format the CXD2303AQ can select six different types of output formats through a combination of the ctl0, ctl1 and ctl2 inputs as shown in the table below. output is synchronized to the sy input signal transition from low to high. table 1. setting values and output formats note that when the sy input is open or low level, the output format is mode #0 (4 : 4 : 4). however, when the sy input signal temporarily goes to low level for the mode switching, the mode changes as shown in timing chart ii . when digital data is being output in the mode n output format, if the sy input signal changes from high level to low level, the digital data continues to be output in the mode n output format for the following two clocks. the output format for the digital data output from the third to fifth clocks is not established, so its use is prohibited. if the sy input signal remains low level, the digital data is output in the mode #0 output format from the sixth clock. after the sy input signal changes from low level to high level, the digital data is output in the mode m output format from the sixth clock. at this time, the data output at the sixth clock is the data a/d converted from the analog input signal that was sampled at the falling edge of the clock input signal immediately after the sy input signal changes from low level to high level. the output format control input signals ctl2, ctl1 and ctl0 are fetched only in sync with the rising edge of the clock input signal after the sy input signal has risen. 8 fft CXD2303AQ ain bin, cin clk an bn cn amp sine wave sg sg 8 8 cross talk measurement circuit note : this diagram shows the case where the channel a is measured. the same as for measuring the channels b and c. setting ctl2 ctl1 ctl0 lll llh lhl lhh hll hlh hhl hhh output mode format 0 4 : 4 : 4 1 4 : 2 : 2 (8 fs) 2 4 : 2 : 2 (d2) 3 4 : 2 : 2 (special) 4 4 : 1 : 1 5 4 : 1 : 1 (special) 6 simple boundary scan 1 7 simple boundary scan 2
14 CXD2303AQ 1.3v n 10 n 9n 8n 4n 3n 2n 1n+1 n 5n 4n 3n 2n 1 n n+1 n+2 n+3 n+4 n+5 n+6 n mode n mode m 2clk 5clk 5clk mode n prohibited mode #0 mode m n+2 clock input sy ctl2 to ctl0 digital output timing chart ii
15 CXD2303AQ mode #0 4 : 4 : 4 bit a 73 sampling timing ( ? ) adc channel adc channel a b c tgr output a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 data a 70 a 71 a 72 a 73 a 74 a 75 a 76 a 77 a 60 a 61 a 62 a 63 a 64 a 65 a 66 a 67 a 50 a 51 a 52 a 53 a 54 a 55 a 56 a 57 a 40 a 41 a 42 a 43 a 44 a 45 a 46 a 47 a 30 a 31 a 32 a 33 a 34 a 35 a 36 a 37 a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 00 a 01 a 02 a 03 a 04 a 05 a 06 a 07 b 70 b 71 b 72 b 73 b 74 b 75 b 76 b 77 b 60 b 61 b 62 b 63 b 64 b 65 b 66 b 67 b 50 b 51 b 52 b 53 b 54 b 55 b 56 b 57 b 40 b 41 b 42 b 43 b 44 b 45 b 46 b 47 b 30 b 31 b 32 b 33 b 34 b 35 b 36 b 37 b 20 b 21 b 22 b 23 b 24 b 25 b 26 b 27 b 10 b 11 b 12 b 13 b 14 b 15 b 16 b 17 b 00 b 01 b 02 b 03 b 04 b 05 b 06 b 07 c 70 c 71 c 72 c 73 c 74 c 75 c 76 c 77 c 60 c 61 c 62 c 63 c 64 c 65 c 66 c 67 c 50 c 51 c 52 c 53 c 54 c 55 c 56 c 57 c 40 c 41 c 42 c 43 c 44 c 45 c 46 c 47 c 30 c 31 c 32 c 33 c 34 c 35 c 36 c 37 c 20 c 21 c 22 c 23 c 24 c 25 c 26 c 27 c 10 c 11 c 12 c 13 c 14 c 15 c 16 c 17 c 00 c 01 c 02 c 03 c 04 c 05 c 06 c 07 low note ( ? ) : see timing chart ii .
16 CXD2303AQ mode #1 4 : 2 : 2 (8 fs) bit a 73 sampling timing ( ? ) adc channel adc channel a b c tgr output a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 data a 70 a 70 a 72 a 72 a 74 a 74 a 76 a 76 a 60 a 60 a 62 a 62 a 64 a 64 a 66 a 66 a 50 a 50 a 52 a 52 a 54 a 54 a 56 a 56 a 40 a 40 a 42 a 42 a 44 a 44 a 46 a 46 a 30 a 30 a 32 a 32 a 34 a 34 a 36 a 36 a 20 a 20 a 22 a 22 a 24 a 24 a 26 a 26 a 10 a 10 a 12 a 12 a 14 a 14 a 16 a 16 a 00 a 00 a 02 a 02 a 04 a 04 a 06 a 06 b 70 b 70 c 70 c 70 b 74 b 74 c 74 c 74 b 60 b 60 c 60 c 60 b 64 b 64 c 64 c 64 b 50 b 50 c 50 c 50 b 54 b 54 c 54 c 54 b 40 b 40 c 40 c 40 b 44 b 44 c 44 c 44 b 30 b 30 c 30 c 30 b 34 b 34 c 34 c 34 b 20 b 20 c 20 c 20 b 24 b 24 c 24 c 24 b 10 b 10 c 10 c 10 b 14 b 14 c 14 c 14 b 00 b 00 c 00 c 00 b 04 b 04 c 04 c 04 b 70 a 70 c 70 a 72 b 74 a 74 c 74 a 76 b 60 a 60 c 60 a 62 b 64 a 64 c 64 a 66 b 50 a 50 c 50 a 52 b 54 a 54 c 54 a 56 b 40 a 40 c 40 a 42 b 44 a 44 c 44 a 46 b 30 a 30 c 30 a 32 b 34 a 34 c 34 a 36 b 20 a 20 c 20 a 22 b 24 a 24 c 24 a 26 b 10 a 10 c 10 a 12 b 14 a 14 c 14 a 16 b 00 a 00 c 00 a 02 b 04 a 04 c 04 a 06 high low high low note ( ? ) : see timing chart ii .
17 CXD2303AQ mode #2 4 : 2 : 2 (d2) bit a 73 sampling timing ( ? ) adc channel adc channel a b c tgr output a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 data a 70 a 71 a 72 a 73 a 74 a 75 a 76 a 77 a 60 a 61 a 62 a 63 a 64 a 65 a 66 a 67 a 50 a 51 a 52 a 53 a 54 a 55 a 56 a 57 a 40 a 41 a 42 a 43 a 44 a 45 a 46 a 47 a 30 a 31 a 32 a 33 a 34 a 35 a 36 a 37 a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 00 a 01 a 02 a 03 a 04 a 05 a 06 a 07 b 70 c 70 b 72 c 72 b 74 c 74 b 76 c 76 b 60 c 60 b 62 c 62 b 64 c 64 b 66 c 66 b 50 c 50 b 52 c 52 b 54 c 54 b 56 c 56 b 40 c 40 b 42 c 42 b 44 c 44 b 46 c 46 b 30 c 30 b 32 c 32 b 34 c 34 b 36 c 36 b 20 c 20 b 22 c 22 b 24 c 24 b 26 c 26 b 10 c 10 b 12 c 12 b 14 c 14 b 16 c 16 b 00 c 00 b 02 c 02 b 04 c 04 b 06 c 06 hiz hiz hiz hiz hiz hiz hiz hiz high low high low high low high low hiz : high impedance note ( ? ) : see timing chart ii .
18 CXD2303AQ mode #3 4 : 2 : 2 (special) bit a 73 sampling timing ( ? ) adc channel adc channel a b c tgr output a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 data a 70 a 71 a 72 a 73 a 74 a 75 a 76 a 77 a 60 a 61 a 62 a 63 a 64 a 65 a 66 a 67 a 50 a 51 a 52 a 53 a 54 a 55 a 56 a 57 a 40 a 41 a 42 a 43 a 44 a 45 a 46 a 47 a 30 a 31 a 32 a 33 a 34 a 35 a 36 a 37 a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 00 a 01 a 02 a 03 a 04 a 05 a 06 a 07 b 70 c 71 b 72 c 73 b 74 c 75 b 76 c 77 b 60 c 61 b 62 c 63 b 64 c 65 b 66 c 67 b 50 c 51 b 52 c 53 b 54 c 55 b 56 c 57 b 40 c 41 b 42 c 43 b 44 c 45 b 46 c 47 b 30 c 31 b 32 c 33 b 34 c 35 b 36 c 37 b 20 c 21 b 22 c 23 b 24 c 25 b 26 c 27 b 10 c 11 b 12 c 13 b 14 c 15 b 16 c 17 b 00 c 01 b 02 c 03 b 04 c 05 b 06 c 07 hiz hiz hiz hiz hiz hiz hiz hiz high low high low high low high low hiz : high impedance note ( ? ) : see timing chart ii .
19 CXD2303AQ mode #4 4 : 1 : 1 bit a 73 sampling timing ( ? ) adc channel adc channel a b c tgr output a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 data a 70 a 71 a 72 a 73 a 74 a 75 a 76 a 77 a 60 a 61 a 62 a 63 a 64 a 65 a 66 a 67 a 50 a 51 a 52 a 53 a 54 a 55 a 56 a 57 a 40 a 41 a 42 a 43 a 44 a 45 a 46 a 47 a 30 a 31 a 32 a 33 a 34 a 35 a 36 a 37 a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 00 a 01 a 02 a 03 a 04 a 05 a 06 a 07 b 70 b 50 b 30 b 10 b 74 b 54 b 34 b 14 b 60 b 40 b 20 b 00 b 64 b 44 b 24 b 04 c 70 c 50 c 30 c 10 c 74 c 54 c 34 c 14 c 60 c 40 c 20 c 00 c 64 c 44 c 24 c 04 hiz hiz hiz hiz hiz hiz hiz hiz hiz hiz hiz hiz high low high low hiz : high impedance note ( ? ) : see timing chart ii .
20 CXD2303AQ mode #5 4 : 1 : 1 (special) bit a 73 sampling timing ( ? ) adc channel adc channel a b c tgr output a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0 data a 70 a 71 a 72 a 73 a 74 a 75 a 76 a 77 a 60 a 61 a 62 a 63 a 64 a 65 a 66 a 67 a 50 a 51 a 52 a 53 a 54 a 55 a 56 a 57 a 40 a 41 a 42 a 43 a 44 a 45 a 46 a 47 a 30 a 31 a 32 a 33 a 34 a 35 a 36 a 37 a 20 a 21 a 22 a 23 a 24 a 25 a 26 a 27 a 10 a 11 a 12 a 13 a 14 a 15 a 16 a 17 a 00 a 01 a 02 a 03 a 04 a 05 a 06 a 07 b 30 b 70 c 32 c 72 b 34 b 74 c 36 c 76 b 20 b 60 c 22 c 62 b 24 b 64 c 26 c 66 b 10 b 50 c 12 c 52 b 14 b 54 c 16 c 56 b 00 b 40 c 02 c 42 b 04 b 44 c 06 c 46 hiz hiz hiz hiz hiz hiz hiz hiz hiz hiz hiz hiz high low high low hiz : high impedance note ( ? ) : see timing chart ii .
21 CXD2303AQ mode #6, 7 simple boundary scan 1 and 2 the CXD2303AQ has a simple boundary scan function. table 2. simple boundary scan bits a7 b7 c7 a6 b6 c6 a5 b5 c5 a4 b4 c4 a3 b3 c3 a2 b2 c2 a1 b1 c1 a0 b0 c0 output data mode #6 mode #7 hl lh hl lh hl lh hl lh note : clk and sy must be set. 2. clamp function the following two points should be noted when using the digital clamp circuit. -the clamp pulse must be supplied externally. -the clamp circuit is not designed for v cycle clamping. 16 different reference levels can be selected for the digital clamp circuit through a combination of the ref0, ref1, ref2 and ref3 inputs as shown in the table below. note that the ref0, ref1, ref2 and ref3 input signals are fetched asynchronously with the clock input signal. table 3. setting values and reference levels setting ref3 ref2 ref1 ref0 llll lllh llhl llhh lhll lhlh lhhl lhhh hlll hllh hlhl hlhh hhl l hhlh hhhl hhhh reference level channel a decimal binary 16 00010000 32 00100000 48 00110000 64 01000000 1 00000001 16 00010000 32 00100000 48 00110000 239 11101111 223 11011111 207 11001111 191 10111111 254 11111110 239 11101111 223 11011111 207 11001111 mode 0 1 2 3 4 5 6 7 8 9 a b c d e f channels b and c decimal binary 128 10000000 128 10000000 128 10000000 128 10000000 1 00000001 16 00010000 32 00100000 48 00110000 127 01111111 127 01111111 127 01111111 127 01111111 254 11111110 239 11101111 223 11011111 207 11001111
22 CXD2303AQ the digital clamp circuit operates in the way the average value of the a/d-converted analog input signal data sampled during the 32 clock cycles after the clamp pulse is input and the reference data set by ref0 to ref3 are compared, and the result difference becomes smaller (see timing chart iii ). therefore, take notice that when there is the fixed noise and others during the 32 cycles of the clock signal, the digital clamp circuit deals with the noise portion as the signal and it comes to the stable state still including the error. photos 1 and 2 show the clamp circuit responses for the application circuit 1. photo 2 shows that inputting the clamp pulse during the vertical hold has no effect on the input signal. 2clk (min.) 32clk clp clk aaaaaaaa aaaaaaaa aaaaaaaa input noise this input level is desired to be clamped. timing iii (when sel=low) photo 1. response waveform of clamp circuit (when f clk =50 msps, clamp pulse is ntsc sync and reference data is 128) upper: analog input pin waveform (h: 5 ms/div., v: 500 mv/div.) lower: analog input signal waveform (h: 5 ms/div., v: 2 v/div.) photo 2. response waveform of clamp circuit (f clk =50 msps, clamp pulse is ntsc sync and reference data is 128) upper: analog input pin waveform (h: 200 s/div., v: 5 v/div.) lower: vertical hold pulse (h: 200 s/div., v: 500 mv/div.)
23 CXD2303AQ reference supply upper data latch upper data latch rbs rb rts rt data0 (lsb) data1 data2 data3 data4 data5 data6 data7 (msb) analog in external clock lower sampling comparator (4bits) lower encoder (4bits) lower sampling comparator (4bits) lower encoder (4bits) upper sampling comparator (4bits) upper encoder (4bits) clock generator fig. 1. 8-bit adc block diagram
24 CXD2303AQ (1) (2) (3) (4) s (1) c (1) s (2) c (2) s (3) c (3) s (4) c (4) md (1) md (2) md (3) md (0) rv (0) rv (1) rv (2) rv (3) s (1) c (1) s (3) h (3) c (3) h (1) ld ( 1) ld (1) c (0) c (2) s (4) h (2) h (4) h (0) ld ( 1) ld (0) s (2) ld (2) data ( 2) data ( 1) data (0) data (1) analog input external clock upper comparators block upper data lower reference voltage lower comparators a block lower data a lower comparators b block lower data b data0 to data7 vi (1) vi (2) vi (3) vi (4) timing chart iv 3. 8-bit adc operation (see fig.1 and timing chart iv ) 1) the CXD2303AQ includes 3 channels of the 8-bit a/d converter. this converter has the 2-step parallel system, composed of a 4-bit upper comparator and two 4-bit lower comparator blocks. the reference voltage that is equal to the voltage between rt-rb/16 is constantly applied to the upper 4-bit comparator block. voltage corresponded to the upper data is fed to the lower 4-bit comparator block through the reference supply . rts and rbs pins serve for the self- generation of rt (reference voltage top) and rb (reference voltage bottom), and they are also used as the sense pins as shown in the application circuit 3.
25 CXD2303AQ 2) this ic uses an offset cancel type comparator that operates synchronously with an external clock. it features the following operating modes which are respectively indicated on the timing chart iv with s, h, c symbols. that is input sampling (auto zero) mode, input hold mode and comparison mode. 3) the operation of respective parts is as indicated in the timing chart iv . for instance the input voltage vi (1) is sampled at the falling edge of the external clock (1) by means of the upper comparator bock and the lower comparator a block. the upper comparator block establishes comparison data md (1) at the rising edge of the external clock (2). simultaneously the reference supply generates the lower reference voltage rv (1) corresponded to the upper results. the lower comparator a block establishes comparison data ld (1) at the rising edge of the external clock (3). md (1) and ld (1) are combined and output as out (1) at the rising edge of the external clock (4). accordingly, there is a 2.5 clock delay from the analog input sampling point to the a/d converter digital data output. note that there is a 4.5 clock delay from the analog input sampling point to the digital data output because the output data selector circuit is located at the stage after the a/d converter circuit. (see the item 5 of notes on operation) notes on operation 1. power supply and ground to reduce the effects of noise, separate the analog and digital systems around the device. bypass both the digital and analog power supply pins to the respective grounds using ceramic capacitors of about 0.1 f set as close to the pin as possible. 2. analog input compared with flash type a/d converters, the input capacitance of the analog input is rather small. however, driving must be performed with an amplifier featuring sufficient bands and drive capability. when driving with an amplifier of low output impedance, parasitic oscillation may occur. this can be prevented by inserting resistance of about 33 ? in series between the amplifier output and a/d input. when the input signals of pins 28, 37 and 66 are monitored, the kickback noise of the clock can be found. however, this has no effect on the a/d conversion characteristics. 3. clock input the clock line wiring should be as short as possible and should be separated from other circuits to avoid any interference with other signals. 4. reference input voltages art to arb, brt to brb and crt to crb supports dynamic range of the analog input. stable characteristics can be obtained by bypassing these pins to gnd using capacitors of about 0.1 f. the self- bias function that generates v rt =about 2.5 v and v rb =about 0.6 v is activated by shorting arts, brts and crts to av dd and arbs, brbs and crbs to av ss , respectively. 5. timing analog input is sampled at the falling edge of clk and output as digital data synchronized with a delay of 4.5 clocks at its rising edge (see timing chart i -3 ). the delay from the clock rising edge to the data output is about 9 ns (dv dd =5 v). 6. output enable pins pins 13 to 20 (a0 to a7) are in the output mode by leaving xaoe open or connecting it to dv ss , and these pins are in the high impedance mode by connecting xaoe to dv dd . pins 3 to 10 (b0 to b7) have the same relationship with xboe, and pins 73 to 80 (c0 to c7) with xcoe, respectively.
26 CXD2303AQ c0 c1 c2 c3 c4 c5 c6 c7 0.1 0.1 33 10 c-ch input 79 78 77 76 75 74 73 72 71 70 69 68 67 66 80 65 0.1 ref3 ref2 ref1 ref0 clp clk sel sy ctl2 ctl1 ctl0 10 0.1 +5v (analog) b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 tgr v dd (digital) 10 0.1 gnd (digital) 0.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 64 63 62 61 60 59 58 57 56 0.1 0.1 33 10 b-ch input 0.1 0.1 0.1 0.1 33 10 a-ch input 0.1 gnd (analog) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 application circuit 1. when clamp and self-bias are used application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
27 CXD2303AQ c0 c1 c2 c3 c4 c5 c6 c7 0.1 0.1 33 c-ch input 79 78 77 76 75 74 73 72 71 70 69 68 67 66 80 65 0.1 clk sy ctl2 ctl1 ctl0 10 0.1 +5v (analog) b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 tgr v dd (digital) 10 0.1 gnd (digital) 0.1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 64 63 62 61 60 59 58 57 56 0.1 0.1 33 b-ch input 0.1 0.1 0.1 0.1 33 a-ch input 0.1 gnd (analog) 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 2. when self-bias is used, and clamp is not used application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
28 CXD2303AQ c0 c1 c2 c3 c4 c5 c6 c7 0.1 0.1 33 c-ch input 0.1 clk sy ctl2 ctl1 ctl0 10 0.1 +5v (analog) b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 tgr v dd (digital) 10 0.1 gnd (digital) 0.1 0.1 0.1 33 b-ch input 0.1 0.1 0.1 33 a-ch input 0.1 gnd (analog) crb 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 64 63 62 61 60 59 58 57 56 crt 79 78 77 76 75 74 73 72 71 70 69 68 67 66 80 65 brb brt 0.1 art arb 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 3. when clamp and self-bias are not used application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
29 CXD2303AQ 40 20 0 25 50 75 85 65 75 70 supply current [ma] ambient temperature [ c] ambient temperature vs. supply current f c =50mhz ntsc ramp wave input av dd =dv dd =5v cle=low 10 20 30 40 50 50 80 supply current [ma] sampling frequency vs. supply current ntsc ramp wave input av dd =dv dd =5v ta=25 c sampling frequency [msps] 200 255075 60 70 65 maximum conversion rate [msps] ambient temperature [ c] ambient temperature vs. maximum conversion rate 40 20 0 25 50 75 85 2 4 3 sampling delay [ns] ambient temperature [ c] ambient temperature vs. sampling delay f c =10mhz av dd =dv dd =5v 110100 0 1 output level [db] analog input frequency [mhz] analog input band 3 0.1 4.75 5 5.25 63 67 65 maximum conversion rate [msps] supply voltage [v] supply voltage vs. maximum conversion rate ntsc ramp wave input av dd =dv dd 0.1 1 25 70 100 85 supply current [ma] input frequency [mhz] input frequency vs. supply current 10 0.01 supply current [ma] supply voltage [v] supply voltage vs. supply current f c =50mhz ntsc ramp wave input av dd =dv dd cle=high ta=25 c f c =50mhz sine wave 1.6vp-p av dd =dv dd =5v ta=25 c cle=low f c =50mhz sine wave 1vp-p input av dd =dv dd =5v ta=25 c f in =1khz, triangular wave input av dd =dv dd =5v 4.75 5 5.25 70 90 80 example of representative characteristics
30 CXD2303AQ 20 0 25 50 75 6 12 output data delay [ns] ambient temperature vs. output data delay ambient temperature [ c] 10 8 40 85 tplh tphl 0.1 1 10 30 50 40 snr [db] analog input frequency [mhz] analog input frequency vs. snr, effective bit 20 0 25 50 75 6 12 output data delay [ns] ambient temperature vs. output data delay ambient temperature [ c] 3 3.5 4 4.5 5 5.5 dv dd supply voltage [v] dv dd supply voltage vs. output data delay 1.5 2.5 80 0 analog input current iai [ma] analog input voltage v in [v] analog input voltage vs. input current 80 0.5 0.1 1 10 40 60 50 sfdr [db] analog input frequency [mhz] analog input frequency vs. sfdr 8 7 6 5 effective bit [bit] 10 8 40 85 tplh tphl 8 12 10 6 output data delay [ns] 510152025 8 12 10 output data delay [ns] load capacitance [pf] load capacitance vs. output data delay 6 0 tplh tphl 510152025 8 12 10 output data delay [ns] load capacitance [pf] load capacitance vs. output data delay 6 0 tplh tphl 14 f c =50mhz av dd =dv dd =5v v in =2vp-p ta=25 c fc=10mhz av dd =5v dv dd =3.3v cl=15pf fc=10mhz av dd =5v dv dd =3.3v ta=25 c f c =50mhz av dd =dv dd =5v vrt=2.5v vrb=0.5v ta=25 c f c =10mhz av dd =5v cl=15pf ta=25 c fc=10mhz av dd =dv dd =5v ta=25 c fc=10mhz av dd =dv dd =5v cl=15pf f c =50mhz av dd =dv dd =5v v in =2vp-p ta=25 c
31 CXD2303AQ 0.1 1 10 30 50 40 cross talk ct [db] input frequency f in [mhz] input frequency vs. cross talk 24 f c =50mhz av dd =dv dd =5v v in =1.6vp-p ta=25 c
32 CXD2303AQ cxd2303q evaluation board evaluation boards are available for the cmos converter CXD2303AQ. block diagram buffers data latch CXD2303AQ analog output analog input external clock clamp pulse +5v gnd 5v digital circuit mount portion cxd1178q 3ch 8-bit dac digital circuit mount portion digit sw analog input interface analog circuit mount portion analog circuit mount portion characteristics resolution 8 bits maximum conversion rate 50 mhz supply voltage 5.0 v (single +5 v power supply possible at self-bias use) supply voltage clock input either 1 or 2 should be used. 1. ttl pulse width t cw1 9 ns (min.) t cw0 9 ns (min.) 2. sine wave item min. typ. max. unit +5 v 185 ma 5 v 20
33 CXD2303AQ analog output (cxd1178q) (rl = 200 ? ) item min. typ. max. unit analog output 1.8 2.0 2.2 v full-scale 0 1.5 3 % output ratio ( ? ) ? full-scale output ratio = full-scale voltage of each channel 1 100 [%] average of the full-scale voltage of each channel output format (CXD2303AQ) the table shows the output format of ad converter. analog input voltage v art , v brt , v crt : : : : v arb , v brb , v crb step 0 : 127 128 : 255 digital output code msb lsb 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 : 0 0 0 0 0 0 0 0 timing chart analog input external clock t pd ( ad ) t pd t pw1 t pw0 1.3v t h t s 1.3v t pd ( da ) 100% 50% 0% ad clock ad output latch output da input da clock da output
34 CXD2303AQ item external clock ( ? ) clock high time clock low time data delay (ad) data delay (latch) setup time hold time propagation delay time (da) symbol t pw1 t pw0 t pd (ad) t dd t s th t pd (da) min. 1 9 9 4.5 5 10 typ. 10 10 max. 1100 1100 11.0 9.5 unit v ns ns ns ns ns ns ns ? in the case of a sine wave, the effects of jitter increase as the input voltage decreases. list of parts resistor r20 75 ? r21 75 ? r30a, b, c 510 ? r31a, b, c 510 ? r32a, b, c 510 ? r33a, b, c 100 k ? r34a, b, c 75 ? r35a, b, c 33 k ? r50 3.3 k ? r51 200 ? r52 200 ? r53 200 ? vr20 2 k ? vr21 2 k ? vr30a, b, v 2 k ? vr31a, b, v 2 k ? vr50 1 k ? transistor q30a, b, c 2sc2785 q31a, b, c 2sc2785 q32a, b, c 2sc2785 ic ic1 CXD2303AQ ic2 74f821 ic3 74f574 ic4 74f574 ic5 74f04 ic6 cxd1178q capacitor c1 0.1 f c2 0.1 f c3 10 f c4 0.1 f c5 0.1 f c6 10 f c7 0.1 f c8 0.1 f c9 0.1 f c10 0.1 f c11 0.1 f c12 0.1 f c13 0.1 f c14 47 f c15 47 f c16 0.1 f c17 0.1 f c20 0.1 f c21 47 f c22 0.1 f c30a, b, c 470 f c31a, b, c 10 f c30a, b, c 0.1 f c50 0.1 f c51 0.1 f c52 0.1 f c53 0.1 f others connector bnc-lr-pc-3 (hirose electric co.,ltd.) dip sw
35 CXD2303AQ b0 b1 b2 b3 b4 b5 b6 b7 a0 a1 a2 a3 a4 a5 a6 a7 tgr arb ain art brt bin brb c7 c6 c5 c4 c3 c2 c1 c0 crt cin cle ref3 ref2 ref1 ref0 sel sy ctl2 ctl1 ctl0 xcoe xboe xaoe ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 bb0 bb1 bb2 bb3 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 19 18 17 16 15 14 13 12 20 10 2 3 4 5 6 7 8 9 11 1 [ic4]74f574 c1 c2 c3 c4 c5 c6 c7 c40c c53 c52 r51 200 c51 r52 200 r53 200 aout bout cout r50 3.3k vr50 1k c50 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 bb7 bb6 bb5 bb4 c2 c2 c0 bb0 bb1 bb2 bb3 bb4 bb5 bb6 bb7 19 18 17 16 15 14 13 12 20 10 2 3 4 5 6 7 8 9 11 1 [ic3]74f574 b1 b3 b4 b5 b6 b7 c40b b2 b0 ab0 ab1 ab2 ab3 ab4 ab5 ab6 ab7 21 20 19 18 17 16 15 14 22 4 5 6 7 8 9 10 [ic2]74f821 a1 a3 a4 a5 a6 a7 11 a2 a0 tgb c40a 23 13 1 3 2 12 24 tgr j8 j15 c6 10 c2 c1 c3 10 c4 c5 c7 c8 c9 c10 j5 c11 crb c17 c16 4 8 10 12 2 6 1 5 3 14 7 c22 [ic5]74f04 vr20 2k vr21 2k 75 r20 75 r21 clamp pulse input 0.1 c20 47 c21 external clock input cle ref3 1 2 ref2 3 ref1 4 ref0 5 sel 6 sy 7 ctl2 8 ctl1 9 ctl0 0 xcoe xboe xaoe 10bit digit sw c14 47 c15 47 analog +5v digital +5v +5v +5v gnd +5v 5v crt vr31c 2k r32c 510 crt adjust crb r30c 510 vr30c 2k q30c q31c r31c 510 crb adjust cin c31c 10 q32c tp30c r34c 75 r33c 100k c30c 470 video signal in c-ch brt adjust brb adjust video signal in b-ch vr31b 2k q31b brb brt r32b 510 q30b r30b 510 vr30b 2k r31b 510 q32b tp30b r35c 33 r35b 33 c31b 10 r34b 75 c30b 470 r33b 100k art adjust arb adjust video signal in a-ch q31a arb art vr31a 2k r32a 510 q30a r31a 510 r30a 510 vr30a 2k bin ain r35a 33 c31a 10 r34a 75 q32a tp30a c30a 470 r33a 100k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 33 34 35 36 25 38 39 40 48 47 46 45 44 43 42 41 37 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 64 63 62 61 60 59 58 57 56 80 79 78 77 76 74 73 72 71 70 69 68 67 66 65 75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 j9 j7 j6 j4 j3 j2 j1 [ic6] cxd1178q (3ch 8-bit dac) [ic1] CXD2303AQ (3ch 8-bit adc) clp clk c12 j14 c13 j13 j11,12 j10 note : unless otherwise specified, all capacitor values are 0.1 f.
36 CXD2303AQ adjustment 1. vref adjustment (vr30, vr31) adjustment of a/d converter reference voltage. arb, brb and crb are adjusted though vr30a, vr30b and vr30c, respectively, and art, arb and crt through vr31a, vr31b and vr31c. when self-bias is used, there is no need for adjustment. reference voltage is set through self-bias delivery. 2. dac output full-scale adjustment (vr50) full-scale voltage of d/a converter output is adjusted to about 2 v at the pcb shipment. 3. clamp pulse and clock signal dc voltage adjustment (vr20, vr21) the clamp pulse and the clock signal dc voltages are adjusted. 4. dip switches all dip switches other than cle are set of off when the pcb is shipped from the factory. only cle is set to on. notes on operation 1. reference voltage when arts, brts and crts are connected to av dd and at the same time arbs, brbs and crbs are connected to av ss , the self-bias function causes the art, brt and crt voltage to become about 2.5 v, and the arb, brb, and crb voltage to become about 0.5 v. on the evaluation board, either self-bias or the external reference voltage can be selected depending on the junction method of the jumper line. when shipped from the factory, the reference voltage is set to self-bias. to select the external reference voltage, adjust the dynamic range (v rt v rb ) to 1.7 vp-p or more. 2. clock input the clock signal should be supplied externally. 3. the three latch ics (74f574, 74f821) are not absolutely necessary for the evaluation of the adc and dac. that is, operation is performed normally if the adc output data is directly input to the dac input. however, as the adc output data is hardly ever d/a converted without executing digital signal processing, it was mounted on the main board to indicate an example layout of digital signal processing ic. use the latch ic output when the adc output data is used. 4. when clamp is not used turning cle to low will set the clamp function off. in this case, the dc element is cut off by means of c31a, c31b and c31c on the main board and dc voltage on the adc side of c31a, c31b and c31c turns to about (v art +v arb ) /2, (v brt +v brb ) /2, and (v crt +v crb ) 2. to transfer dc elements of input signals, short c31a, c31b and c31c. at that time, it is necessary to bias input signals, but keeping r34a, r34b and r34c open, q32a, q32b, q32c can also be used as buffer. use the open space for the bias circuit. 5. clamp pulse latch the latch is incorporated in the clp pin of the CXD2303AQ. 6. peripheral through hole there is a group of through holes on the analog input, output and logic. they are to be used when mounting additional circuits to the evaluation board. use when necessary. the connector hole on the dac part is used to mount the test chassis mount jack.
package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 0.1 + 0.15 14.0 0.1 + 0.4 17.9 0.4 16.3 0.1 0.05 + 0.2 2.75 0.15 + 0.35 0.8 0.2 0.15 0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0 to 10 detail a a package outline unit : mm CXD2303AQ 37
38 CXD2303AQ sony corporation package structure sony code eiaj code jedec code qfp-80p-l01 qfp080-p-1420 package material lead treatment lead material package mass epoxy resin solder plating 42/copper alloy 1.6g 23.9 0.4 20.0 0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 0.1 + 0.15 14.0 0.1 + 0.4 17.9 0.4 16.3 0.1 0.05 + 0.2 2.75 0.15 + 0.35 0.8 0.2 0.15 0.05 + 0.1 80pin qfp (plastic) m 0.2 0.15 0 to 10 detail a a package outline unit : mm lead specifications item lead material alloy 42 lead treatment sn-bi 2.5% lead treatment thickness 5-18 m spec.

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